1. Field of the Invention
The present invention relates generally to a method of manufacturing a semiconductor device, and more particularly, to a metallization method and a method of etching a metal layer using an etching gas that includes Cl2 and N2, and an etching gas formed of Cl2 and N2.
2. Description of the Related Art
As semiconductor devices become highly integrated, the line width of metal interconnection layers of multilevel metal interconnection structures and the distance between adjacent metal interconnection layers have been reduced while the height of the metal interconnection layers has been increased to increase the aspect ratio. In these semiconductor devices, the metal interconnection layers electrically connect unit devices. The metal interconnection layer may be formed of a material that has a low resistance in order to obtain devices that can operate at a high speed. Aluminum or an aluminum alloy may be used to form the metal interconnection layers.
Although aluminum has excellent electric conductivity, the difference between the etching selectivity of aluminum and the etching selectivity of a photoresist material is small. As a result, the thickness of the photoresist layer is increased. However, when the thickness of the photoresist layer is increased, the throughput of the semiconductor device decreases, and it can become difficult to pattern the photoresist layer. When the thickness of the photoresist layer pattern is reduced to avoid these problems, the regions that are to be protected when patterning the metal interconnection layers cannot be protected. Technology has been developed that uses a hard mask when forming aluminum interconnection layers so that micro-sized metal interconnection patterns for the highly-integrated semiconductor device may be formed.
In an etching process for forming metal interconnection layers that uses a hard mask, a reaction by-product may be formed which may be removed during the etching process or may be deposited on the inner walls of the etching chamber. However, if the reaction by-product is not firmly attached to the inner walls of the etching chamber, the reaction by-product may fall to the surface of a wafer during the etching process, which may cause short circuits between the metal interconnection patterns.
In one conventional method that uses a hard mask to form the metal interconnection layers, the etching gas includes at least one fluorocarbon-based gas such as CF4 or CHF3, as well as Cl2 and BCl3, which have been used in conventional processes where a photoresist layer is used as the etch mask. The fluorocarbon-based gases are used for the passivation of the sidewalls of the metal interconnection patterns. When a fluorocarbon-based gas is used in the etching gas, a by-product deposition layer having low adhesive characteristics may be created in the form of flakes located on the inner walls of the etching chamber. Because the by-product has low adhesive characteristics, the by-product may fall onto the wafer's surface during the etching process. Thus, the number of particles (e.g., contaminants) present on the wafer surface may increase, which reduces yield.
In another conventional method, an etching gas of Cl2/BCl3/N2 is formed by using N2 as a passivation gas instead of a fluorocarbon-based gas, which, as described above, may cause the generation of particles in the etching chamber. However, when this etching gas is used, cone-shaped defects occur on the semiconductor wafer due to the presence of BCl3.
In addition, as the aspect ratio of the metal interconnection patterns increases in a highly-integrated semiconductor device, micro-loading may occur. In particular, micro-loading may vary the etching rate according to the pattern density of regions of a chip on the wafer or may vary the profile shape of the patterns due to a difference in the critical dimension (CD) between a top sectional profile and a bottom sectional profile of the patterns. As the line width of the metal interconnection patterns is reduced, defects may occur due to the micro-loading, which may cause failures in the semiconductor device.